`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:09:40 07/09/2015 
// Design Name: 
// Module Name:    MemoriaInstruccionesB 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MemoriaInstruccionesB(
	input clk,
	input [31:0] InstAddr,
	output reg [31:0] Inst
    );

reg [31:0] memoria[127:0];
//                | OP |
initial begin
	memoria[0] = 32'b 00100000000010100000000000001111;
	memoria[1] = 32'b 00100000000010110000000000001010;
end


always@(posedge clk) begin
	if(InstAddr < 128) Inst = memoria[InstAddr/4];
	//else douta = memoria[0];
end

endmodule
